1. Field of the Invention
The present invention relates to a dual gate oxides"" process for mixed-mode IC. More particularly, the present invention relates to a dual gate oxides"" process for mixed-mode IC, which protects and improves the dual gate oxides"" quality.
2. Description of the Prior Art
The conventional mixed-mode IC includes embedded dynamic random access memory (embedded DRAM), embedded static random access memory (embedded SRAM) and application-specific integrated circuit (ASIC) In a mixed-mode IC there are at least two types of transistor devices, for example, memory devices and logic devices. For mixed-mode IC, each type of transistor device requires different gate operational voltages. Therefore, it is required to form different kinds of transistor devices with different gate oxide thickness on a same chip. For example, a device such as a memory device having a gate oxide thickness of about 50 angstroms, the gate operational voltage is about 25V. For a device such as a peripheral circuit device having a gate oxide thickness of about 70 angstroms, the gate operational voltage is about 33V. For a device such as a high voltage device having a gate oxide thickness of about 120 angstroms, the gate operational voltage is about 5.0V.
As shown in FIGS. 1A and 1B, the conventional process to make different gate oxide with different thickness on the same substrate comprises the steps for forming a first gate oxide layer 101 on a semiconductor substrate 100 through thermal oxidation, and then forming a photoresist 102 on the first gate oxide layer 101 while exposing a portion of the first gate oxide layer 101 then removing the exposed portion of the first gate oxide layer 101 by wet etching with buffered oxide etches (BOE) or HF dip etching. Then the photoresist 102 is stripped away. Thereafter, forming a second gate oxide layer 103 thinner than the first gate oxide layer 101 on the substrate 100 through thermal oxidation, upon the second gate oxide layer 103 growing, a gate oxide also grows on the first gate oxide layer 101 at a slower rate. Finally, the total thickness of the first gate oxide layer 101 is thicker than that of the second gate oxide layer 103.
The photoresist 102 can be stripped away by way of a wet stripping method utilizing an organic solution or an Inorganic solution, or a dry stripping method with oxygen plasma. However, the photoresist 102 is directly in contact with the first gate oxide layer 101, the photoresist 102 readily contaminates the first gate oxide layer 101, in spite of the process for stripping away the photoresist 102.
Accordingly, it is desirable to provide a method for forming a dual gate oxides"" structure, which can overcome the drawback of the prior art and improve the dual gate oxides"" quality.
It is one object of the present invention to provide a method for fabricating semiconductor devices with dual gate oxides which protect the dual gate oxides from coming directly in contact with a photoresist, and then avoiding the photoresist contamination on the dual gate oxides.
It is another object of the present invention to provide a method for fabricating semiconductor devices with dual gate oxides which improves the dual gate oxides"" quality.
In order to achieve the above objects, the present invention provides a method for fabricating semiconductor devices with dual gate oxides. Firstly, a semiconductor substrate is provided followed by forming a first gate oxide on the substrate. Next, forming a first conductive layer on the first gate oxide, and then forming a photoresist on the first conductive layer while exposing a portion of the first conductive layer. Subsequently, removing the exposed portion of the first conductive layer and the first gate oxide thereunder. Thereafter, forming a second gate oxide thinner than the first gate oxide on the first conductive layer on the first gate oxide and on the substrate. Following, forming a second conductive layer on the second gate oxide and then forming a protecting layer on the second conductive layer. Defining a first active area over the second gate oxide on the substrate. After that, respectively, forming a trench between the first active area and the second active area and beside another respective side of the first active area and the second active area. Then, forming a dielectric layer over the first active area and the second active area to fill the trench. Planarizing the dielectric layer until exposing the second conductive layer over the first active area while the rest of the protecting layer is left on the second conductive layer of the second active area. Then, sequentially removing the exposed second conductive layer and the second gate oxide thereunder over the first active area. Subsequently, removing the rest of the protecting layer over the second active area. Finally, forming a third conductive layer over the substrate, and patterning the third conductive layer to respectively form a conductive gate on the second gate oxide of the second active area. Thereby, a dual gate oxides"" structure is obtained. The first conductive layer and the second conductive layer are respectively formed on the first gate oxide and the second gate oxide, therefore, the first gate oxide and the second gate oxide are protected from coming directly in contact with the respective photoresist. And then, the photoresist contamination on the dual gate oxides is avoided.